Method for Reducing Timing Libraries for Intra-Die Model in Statistical Static Timing Analysis

摘要

A method for performing statistical static timing analysis on an integrated circuit (IC) is disclosed, which comprises identifying a plurality of turned-on devices in the IC during a predetermined operation of the IC, choosing only the libraries of the plurality of turned-on devices, and calculating a time delay of the IC using only the chosen libraries, wherein the number of libraries used for the time delay calculation is reduced.