| 摘要 |
<p>A system comprises a first interconnect matrix coupled to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports. A second interconnect matrix is coupled to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports. A shared multiport controller is coupled to at least one slave port of the first interconnect matrix and to at least one master port of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix.</p> |
