发明名称 POWER REMAINDER COMPUTING UNIT AND ITS CONTROL METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To solve a problem of enlarging a circuit scale in the conventional power remainder computing units. <P>SOLUTION: This power remainder computing unit has a multiplication remainder computing unit 21 carrying out multiplication operation and remainder operation based on a multiplicand, a multiplier and a divisor; a power number storage part for individually storing each bit value when showing a power number as a binary number; a first selecting circuit 22 outputting either one of the output of the multiplication remainder computing unit 21 and the multiplicand according to the bit value to be referred to; and a result storage register 26 storing the output value of the first selecting circuit 22 as a computed result. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009008993(A) 申请公布日期 2009.01.15
申请号 JP20070171831 申请日期 2007.06.29
申请人 NEC ELECTRONICS CORP 发明人 FUKAZAWA HIROSHI
分类号 G09C1/00 主分类号 G09C1/00
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