发明名称 METHOD AND DEVICE FOR INSPECTION AND FAILURE ANALYSIS DEVICE
摘要 PROBLEM TO BE SOLVED: To discriminate an abnormality of a chip, even when a supply current of a normal chip is heavy. SOLUTION: This device is equipped with a sample stand 4 for loading an LSI chip 1 thereon; a test pattern generator 3 for supplying a test pattern to the LSI chip 1 through the sample stand 4; an optical system 5 with a laser modulation function for irradiating the LSI chip 1, while scanning with a modulated laser beam 8; an IR-OBIRCH control part 6 for taking out a signal from the LSI chip 1 through a lock-in amplifier for taking out only a signal having a prescribed frequency by a signal from the LSI chip 1, and performing image processing for allowing the taken-out signal to correspond to a scanning point; and a display part 7 for displaying an image based on an image signal from the IR-OBIRCH control part 6. The IR-OBIRCH control part 6 confirms existence of an abnormal current path in the LSI chip 1 based on the image signal. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009008627(A) 申请公布日期 2009.01.15
申请号 JP20070172555 申请日期 2007.06.29
申请人 NEC ELECTRONICS CORP 发明人 FUTAGAWA KIYOSHI
分类号 G01R31/302 主分类号 G01R31/302
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