Serial-to-parallel conversion circuit and method of designing the same

摘要

The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data (D) and a strobe (S) when a first-stage memory device (10a,20a) in a shift register (SF1,SF2) latches data and when the memory device holds the data; providing a logical circuit (30,40) for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.