| 摘要 |
A semiconductor integrated circuit is provided to prevent data collision in the test mode by operating to a global input output line corresponding to a predetermined bank in response to a control signal of a control circuit. In a semiconductor integrated circuit, a control signal generating part(112) produces a control signal(RD01, RD23, RD45) in response to the column control signal(Y0) and test mode signal(TPARA). The control signal generating part activates the first control signal in response to an activated test mode signal and column control signal, and it supplies the activated first control signal in response to the column control signal activated in the test mode. The control signal generating part comprises a plurality of inverters(IV1-IV5) and plurality of the NAND gate(ND1,ND2). |
