| 摘要 |
A semiconductor memory apparatus is provided to feed back a clock signal of which duty ratio is regularly controlled by utilizing the delay locking circuit. In a semiconductor memory apparatus, a delay locked loop(300) outputs the clock signal(RDLLCLK, FDLLCLK) having delay having the timing which precedes the inputted clock signal(CLK, CLKB) is outputted. The analog duty correction circuit(400) controls output drivers(340, 350) of the delay locked loop in order to accurately control the duty ratio of the delayed locked clock signal. Outputted data is synchronized with the fixed clock signal. The stable operation outside of the semiconductor memory device is performed stably by using data synchronized to the system clock signal. |
