发明名称 |
Adaptable data path for synchronous data transfer between clock domains |
摘要 |
Systems and methods for implementing synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.
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申请公布号 |
US7477712(B2) |
申请公布日期 |
2009.01.13 |
申请号 |
US20050118632 |
申请日期 |
2005.04.29 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
FISCHER TIMOTHY C.;NAFFZIGER SAMUEL;PATELLA BENJAMIN J. |
分类号 |
H04L7/02 |
主分类号 |
H04L7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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