| 摘要 |
A high input voltage tolerant input/output circuit includes a pad, a clamping circuit clamping a high voltage applied to the pad to generate a clamping signal, and a buffer unit transmitting an input signal received by the pad to an internal circuit and outputting data of the internal circuit to the pad in response to the clamping signal. The buffer unit includes stacked NMOS transistors. When a high voltage higher than a power supply voltage is applied to the pad, the stacked NMOS transistors are turned on, and the stacked NMOS transistors are prevented from being destroyed by the high voltage. When an electrostatic discharge voltage is applied to the pad, the stacked NMOS transistors are turned off, and the stacked NMOS transistors are prevented from being destroyed by electrostatic discharge current.
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