发明名称 Defect tolerant redundancy
摘要 Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit configuration wherein functional circuit blocks in a group of circuit blocks are selected by multiplexers. Multiplexers at the input and output of the group of circuit blocks steer input and output signals to and from functional circuit blocks, avoiding circuit blocks found to be defective or nonfunctional. Multiple groups of these circuit blocks may be arranged in series and in parallel. Alternate multiplexer configurations may be used in order to provide a higher level of redundancy. Other embodiments use all functional circuit blocks and sort integrated circuits based on the level of functionality or performance. Other embodiments provide methods of testing integrated circuits having one or more of these circuit configurations.
申请公布号 US7477091(B2) 申请公布日期 2009.01.13
申请号 US20050105326 申请日期 2005.04.12
申请人 NVIDIA CORPORATION 发明人 NICKOLLS JOHN R.
分类号 G06F11/16;G06F11/20;G11C29/00 主分类号 G06F11/16
代理机构 代理人
主权项
地址