| 摘要 |
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip (102) comprising an exposed backside surface (110) defining a plane, a plurality of wire bonds (106) that are conductively coupled to the integrated circuit chip (102), each of the plurality of wire bonds (106) being conductively coupled to a conductive exposed portion (108), a portion of the conductive exposed portion (108) being positioned in the plane defined by the backside surface (110), and an encapsulant material (105) positioned adjacent the integrated circuit chip (102) and the plurality of wire bonds (106). |
