| 摘要 |
A NAND flash memory device is provided to reduce the number of serially connected memory cells to the half in one string, so reducing the channel length. A first string comprises a first drain selecting transistor(DSTo), a first group memory cell transistor(the MC0 o or the MC15 o) and source select transistor(SSTo). The first drain selecting transistor is serially connected between the common bit line(BL0) and common source line. The second string comprises a second drain selection transistor(DSTe), a second group memory cell transistor(the MC0 e or the MC15 e) and the second source select transistor(SSTe). The second drain selection transistor is serially connected between the common bit line and common source line. |
