| 摘要 |
A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one of the output signals is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when the one of the output signals of the AND plane is inactivated. The PLA uses a reset signal as a driving signal, instead of a clock signal. Accordingly, it is possible to realize a PLA with both low power consumption and high operation speed.
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