发明名称 |
Method for improved single event latch up resistance in an integrated circuit |
摘要 |
A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
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申请公布号 |
US7474011(B2) |
申请公布日期 |
2009.01.06 |
申请号 |
US20060527374 |
申请日期 |
2006.09.25 |
申请人 |
INTEGRATED DEVICE TECHNOLOGIES, INC. |
发明人 |
LIEN CHUEN-DER;TIEN TA-KE;HUANG PAO-LU LOUIS |
分类号 |
H01L27/00;G06F17/50 |
主分类号 |
H01L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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