发明名称 |
Multi-threaded processor having compound instruction and operation formats |
摘要 |
A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction format in which a single instruction comprises multiple operation fields, with one or more of the operation fields each comprising at least an operation code field and a function field. The operation code field and the function field together specify a particular operation to be performed by one or more of the execution units.
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申请公布号 |
US7475222(B2) |
申请公布日期 |
2009.01.06 |
申请号 |
US20050096767 |
申请日期 |
2005.04.01 |
申请人 |
SANDBRIDGE TECHNOLOGIES, INC. |
发明人 |
GLOSSNER C. JOHN;HOKENEK ERDEM;MOUDGILL MAYAN;SCHULTE MICHAEL J. |
分类号 |
G06F15/16;G06F9/30;G06F9/38 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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