A system and method for generating global asynchronous signals in a computin g structure. Particularly, a global interrupt and barrier network is implement ed that implements logic for generating global interrupt and barrier signals fo r controlling global asynchronous operations perfomed by processing elements a t selected processing nodes (12) of computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes (12) for communicating the global interrupt and barrier signals to the elements via low latency paths. The global asynchronous signa ls respectively initiate interrupt and barrier operations at the processing nod es (12) at times selected for otpimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structur e comprising a plurality of processing nodes interconnected by multiple independent networks.
申请公布号
CA2437035(C)
申请公布日期
2009.01.06
申请号
CA20022437035
申请日期
2002.02.25
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
COTEUS, PAUL W.;CHEN, DONG;BLUMRICH, MATTHIAS A.;GARA, ALAN G.;HEIDELBERGER, PHILIP;TAKKEN, TODD E.;GIAMPAPA, MARK E.;STEINMACHER-BUROW, BURKHARD D.;KOPSCAY, GERARD V.