| 摘要 |
A PLL frequency synthesizer circuit includes a voltage-controlled oscillator circuit provided with a capacitor, an inductor, and a variable capacitor element oscillating using the resonance frequencies of the capacitor and inductor, for outputting the oscillation frequency signal of a variable capacitor element, a negative feedback loop circuit capable of looping the signal output from the voltagecontrolled oscillator circuit and performing a frequency acquisition operation for adjusting the frequency of the signal to a desired locking frequency, a tuning circuit for performing tuning so that the oscillation frequency approaches the locking frequency, by modulating the capacitance value of the capacitor of the voltage-controlled oscillator circuit prior to the frequency acquisition operation, and a reference potential application circuit for applying a reference potential to the variable capacitor element of the voltage-controlled oscillator circuit during the tuning operation performed by the tuning circuit. |
