发明名称 |
Techniques For Generating Bit Reliability Information In The Post Processor |
摘要 |
A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.
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申请公布号 |
US2009006930(A1) |
申请公布日期 |
2009.01.01 |
申请号 |
US20070771226 |
申请日期 |
2007.06.29 |
申请人 |
HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS, B.V. |
发明人 |
DJURDJEVIC IVANA;GALBRAITH RICHARD LEO;WILSON BRUCE ALEXANDER;LEE YUAN XING;OENNING TRAVIS ROGER;BLAUM MARIO;LAKOVIC KSENIJA;LI ZONGWANG |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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