发明名称 Semiconductor device with reduced fringe capacitance
摘要 In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.
申请公布号 US2009001474(A1) 申请公布日期 2009.01.01
申请号 US20070823892 申请日期 2007.06.29
申请人 发明人 DATTA SUMAN;RAKSHIT TITASH;KAVALIEROS JACK T.;DOYLE BRIAN S.
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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