发明名称 Biasing scheme for large format CMOS active pixel sensors
摘要 An image sensor includes circuitry compensating for voltage drops in a VSS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the VSS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations.
申请公布号 US2009002536(A1) 申请公布日期 2009.01.01
申请号 US20080216430 申请日期 2008.07.03
申请人 发明人 NAKAMURA JUNICHI;TAKAYANAGI ISAO
分类号 G09G3/20;H04N3/15;H04N5/359;H04N5/374;H04N5/378 主分类号 G09G3/20
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