发明名称 Native Composite-Field AES Encryption/Decryption Accelerator Circuit
摘要 A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).
申请公布号 US2009003589(A1) 申请公布日期 2009.01.01
申请号 US20070771723 申请日期 2007.06.29
申请人 MATHEW SANU;SHEIKH FARHANA;KRISHNAMURTHY RAM 发明人 MATHEW SANU;SHEIKH FARHANA;KRISHNAMURTHY RAM
分类号 H04L9/28 主分类号 H04L9/28
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