发明名称 Reference voltage generating circuit
摘要 Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
申请公布号 US2009002048(A1) 申请公布日期 2009.01.01
申请号 US20080230489 申请日期 2008.08.29
申请人 ELPIDA MEMORY, INC. 发明人 FUJISAWA HIROKI;NAKAMURA MASAYUKI;TANAKA HITOSHI
分类号 H03L5/00 主分类号 H03L5/00
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