| 摘要 |
<p>A system and method for automatic correction of voltage drop (IR Drop violations) of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness, are disclosed. The method includes analyzing polygons or signals for voltage drop violations, in a mask layout block and obtaining one or more voltage drop restriction information associated with polygons or signals from a technology and an external constraints file. The system automatically corrects all voltage drop violations if found, changing polygons space, width and length. The method also includes analysis and automatic correction of contacts and VIA'S according to amount and location in order to comply with voltage drop requirements as taken from technologyor external constraints file. The method provides a violation marker associated with position of polygons or signals that graphically represents a width, space, length violation.</p> |
