发明名称 |
METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS |
摘要 |
METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
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申请公布号 |
SG148153(A1) |
申请公布日期 |
2008.12.31 |
申请号 |
SG20080081762 |
申请日期 |
2006.03.06 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD |
发明人 |
WAY TEH YOUNG;MENG LEE YONG;WOH LAI CHUNG;WENHE LIN;YONG LIM KHEE;LENG TAN WEE;SUDIJONO JOHN;PENG KOH HUI;CHOO HSIA LIANG |
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