发明名称 DATA OUTPUT CONTROLLER
摘要 A data output controller including control signal generating part and latch part is provided to prevent a malfunction of a data output by reducing influence about delay between internal signals although a pulse width of an external clock is changed. A data output controller(10) comprises a control signal generating part(20) and a latch part(30). The control signal generating part generates a control signal using a first clock signal, and includes a delay part and an operation part. The latch part latches by synchronizing an inputted data signal to the control signal. The first clock signal is generated by using a rising clock of an external clock.
申请公布号 KR20080114404(A) 申请公布日期 2008.12.31
申请号 KR20070063929 申请日期 2007.06.27
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KANG, TAE JIN
分类号 G11C7/10;G11C7/22 主分类号 G11C7/10
代理机构 代理人
主权项
地址