发明名称 Apparatus and method for memory encryption with reduced decryption latency
摘要 A method and apparatus for memory encryption with reduced decryption latency. In one embodiment, the method includes reading an encrypted data block from memory. During reading of the encrypted data block, a keystream used to encrypt the data block is regenerated according to one or more stored criteria of the encrypted data block. Once the encrypted data block is read, the encrypted data block is decrypted using the regenerated keystream. Accordingly, in one embodiment, encryption of either random access memory (RAM) or disk memory is performed. A keystream is regenerated during data retrieval such that once the data is received, the data may be decrypted using a single clock operation. As a result, memory encryption is performed without exacerbating memory latency between the processor and memory.
申请公布号 US7472285(B2) 申请公布日期 2008.12.30
申请号 US20030603680 申请日期 2003.06.25
申请人 INTEL CORPORATION 发明人 GRAUNKE GARY L.;ROZAS CARLOS
分类号 H04L9/00;G06F12/08;G06F12/14;G06F21/00 主分类号 H04L9/00
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