发明名称 STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF
摘要 <p>A stacked semiconductor package and a manufacturing method thereof are provided to solve an electrical contact defect between semiconductor chips. A stacked semiconductor package(100) comprises a semiconductor chip module(200), a conductivity growth layer(300) a base substrate(400) and a molding material(500). The semiconductor chip module comprises laminated semiconductor chips(210,220,230,240) in which via holes(215,225,235,245) which are mutually arranged are formed. The conductivity growth layer is arranged inside the arranged via holes. The conductivity growth layer is grown up according to the via holes. The base substrate supports the semiconductor chip module. The base substrate comprises a substrate body(410), a connection pad(420), and a voland(430) and a solder ball(440).</p>
申请公布号 KR20080112627(A) 申请公布日期 2008.12.26
申请号 KR20070061246 申请日期 2007.06.21
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, SUNG MIN
分类号 H01L23/12 主分类号 H01L23/12
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