发明名称 Semi-flattened pin optimization process for hierarchical physical designs
摘要 In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
申请公布号 US7469399(B2) 申请公布日期 2008.12.23
申请号 US20060531398 申请日期 2006.09.13
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BERRY CHRISTOPHER J.;CARNEY CHRISTOPHER M.;RUDE DAVID L.;ST. JUSTE EDDY
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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