| 摘要 |
PROBLEM TO BE SOLVED: To provide a structure for considerably reducing an area overhead, in a semiconductor integrated circuit of test configuration that uses a partial rotation type scanning circuit. SOLUTION: The semiconductor integrated circuit of test configuration comprises a combination circuit 3 and a scan chain 2, configured by chain connection of a plurality of scan flipflops 5. The scan chain 2 is divided into a plurality of partial scan chains 20a-20n, and each of the partial scan chains 20a-20n comprises a partial rotation type scan (PRS) function and a test response compression (MISR) function. A scan test is carried out in a plurality of steps, by changing a combination of the partial scan chains set as PRS and the partial scan chains set as MISR. A test can thereby be carried out, without having to provide a test response compressor separately from the scan chain so that the area overhead is reduced. COPYRIGHT: (C)2009,JPO&INPIT
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