| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent a multi-core processor system which uses two types of TAP controllers from being erroneously operated. <P>SOLUTION: A chip 1 is provided with a first TAP controller 10 for analyzing n bits smaller in number than the total number m (m≥2) in a bit column in a group 1 having an m bit length as an instruction to perform processing to an object of control, and for analyzing each bit column having the m bit length constituted by adding one predetermined bit column to each bit column in the group 1 constituted of at least two or more bit columns each having an n bit length as an instruction not to perform processing to the object of control; and a second TAP controller 20 for analyzing each bit column in a group 2 as an instruction, and for extracting and analyzing one bit column having the n bit length showing an instruction not to perform processing to the object of control from each bit column to be analyzed as an instruction to perform processing to the object of control by the TAP controller 10 in the bit column in the group 1. <P>COPYRIGHT: (C)2009,JPO&INPIT |
