发明名称 INFORMATION PROCESSOR, CACHE FLUSH CONTROL METHOD AND INFORMATION PROCESSING CONTROLLER
摘要 PROBLEM TO BE SOLVED: To provide an information processor, a cache flush control method and an information processing controller to improve a data processing speed, by efficiently carrying out the cache flush of a cache memory. SOLUTION: A CPU 20 is provided with a load/store unit 22 and a flush control section 23. In addition, the CPU 20 controls data stored in a cache 32 via a cache controller 31. When the flush control section 23 detects a signal ".f", an access is waited for one cache line. Moreover, when the access for one cache line is detected, the flush control section 23 issues a cache flush instruction to the cache controller 31. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008305246(A) 申请公布日期 2008.12.18
申请号 JP20070152896 申请日期 2007.06.08
申请人 FREESCALE SEMICONDUCTOR INC 发明人 NAGANO KAZUHIRO
分类号 G06F12/08;G06F9/38 主分类号 G06F12/08
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