| 摘要 |
An exemplary TFT array substrate includes an insulating substrate, a gate electrode provided on the insulating substrate, a gate insulating layer covering the gate electrode and the insulating layer, an amorphous silicon (a-Si) pattern formed on the gate insulating layer, a heavily doped a-Si pattern formed on the a-Si pattern, a source electrode formed on the gate insulating layer and the heavily doped a-Si pattern and a drain electrode formed on the gate insulating layer and the heavily doped a-Si pattern. The source electrode and the drain electrode are isolated by a slit formed between the source electrode and the drain electrode, and the a-Si pattern includes a high resistivity portion corresponding to the slit whose resistance is higher than a resistance of the a-Si material.
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