Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.
申请公布号
WO2008154625(A2)
申请公布日期
2008.12.18
申请号
WO2008US66690
申请日期
2008.06.12
申请人
RAMBUS INC.;CLINE, JULIA, V. M.;HO, EUGENE, C.;STOTT, BRET, G.;WARE, FREDERICK, A.
发明人
CLINE, JULIA, V. M.;HO, EUGENE, C.;STOTT, BRET, G.;WARE, FREDERICK, A.