| 摘要 |
PROBLEM TO BE SOLVED: To solve a cell layout mistake and increment in the number of steps required for layout that has never been generated in the automatic layout in the case that when the I/O cells generated by POE technology are arranged interdigitately, automatic layout using a layout tool is impossible, manual layout is therefore required, and a designer is required to manually change the layout each time when arrangement of I/O cells, changes in kinds of chip and size thereof are changed. SOLUTION: In the chip layout design method, the I/O cells are arranged in a plurality of steps in the periphery of a semiconductor chip in the internal and external direction for the circumferential edge. For a plurality of kinds of the I/O cells to be mounted on the semiconductor chip, each I/O cell is replaced with a dummy common library cell having combined input/output terminal locations of the I/O cells in a non-overlapping state, and having a cell size covering the entire part of the layout area of the plurality of kinds of the I/O cells and the common library cells are arranged using an automatic layout tool. COPYRIGHT: (C)2009,JPO&INPIT
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