| 摘要 |
A gain switching determination circuit (250) compares/determines a comparative input voltage (Vc) from an inter-stage buffer (230) with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (210, 220), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.
|
