Fault testing of logic circuits

摘要

A method and apparatus for detecting faults in logic circuits requires the retention of a single binary reference word for each circuit type to be tested. Responsive to a sequence of input binary words preselected to reveal potential faults of the circuit under test, a single binary word is derived, as a figure of merit, by adding the sequence of output binary words produced by the circuit under test. Comparison of the single binary word generated by the circuit under test with the reference binary word which is characteristic of a properly functioning circuit of the same type provides the desired fault indication. Economies of time and apparatus are thus realized.