ANALYTICAL APPARATUS

摘要

1416102 Image analysis apparatus ROBERT BOSCH FERNSEHANLAGEN GmbH 10 May 1973 [10 May 1972] 22365/73 Heading G1A A heterogeneous material is analysed in two dimensions by raster scanning the material to develop a video signal, applying the latter to a discriminator and developing a dot raster binary signal by clocking, the developed signal being applied to a series of delay and gating circuits which have the effect of scanning a notional two dimensional element (which can be of e.g. hexagonal, parrallelogram or straight line form) line by line over the material. Grain size analysis is then possible by erosion (when all dots within the element are high, output of circuit is high, so that all grains below element size are suppressed) or dilatation (or amplification) (when only one dot has to be high to give a high output signal). Combinations of erosion/dilatation are also possible. To produce a regular hexagonal element, the circuit of Fig. 2 (not shown) is used, which comprises a sequence of delay stages, for delaying the signal equally in three directions r 1 , r 2 , and r 3 , but for variation in the size and shape of the element, the circuit of Fig. 4 is used. The general principle involves a first delay device 9 which delays by n 1 times one dot raster period, a second 10 for delaying by n 2 lines plus n2/2 dot raster periods and a third 11 for delaying by n 3 minus n3/2 dot raster periods. Also included are AND gates 18, 19, 20 for combining the direct and delayed signals. This circuit effects erosion; for dilatation, negation stages are added, Fig. 5 (not shown); for combination techniques, switches are also provided, Fig. 6. (not shown) The system operates in association with interfaced raster scanning which repeats every four frames, Figs. 1, 8 (not shown). The first delay stage (r 1 direction) is effected by a shift register which is clocked, which is such as to alternate the start of the lines by ¢ dot raster period from one line to the next. Delay in the r 2 and r 3 directions is effected by a shift registers associated with flip flops, under the control of the clock and a further regular clock pulse series. Further modifications of these delay circuits are described with reference to Figs. 12, 14 and 15. (not shown). The use of MOS shift registers, connected in parallel is described, Fig. 16.(not shown).