发明名称 |
DIGITAL PHASE SYNCHRONOUS LOOP |
摘要 |
PURPOSE:To obtain the n-fold or 1/n-fold frequency with the sine wave value at each sampling point of the phase synchronous loop, by providing a circuit which performs n-fold or 1/n-fold multiplication for the phase disignation signal and quantizing the output of the above circuit to turn it into the address signal. |
申请公布号 |
JPS5394167(A) |
申请公布日期 |
1978.08.17 |
申请号 |
JP19770007760 |
申请日期 |
1977.01.28 |
申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
YAHATA MEIKI;MURAKAMI JIYUNZOU |
分类号 |
H03L7/16;H03B28/00;H03D1/22;H03L7/00;H03L7/06 |
主分类号 |
H03L7/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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