| 摘要 |
PURPOSE:To reduce the total number of the address which form the multiplier by giving the shift process to the input signal based on the coefficient block number of the plural bits, and thus to simplify the constitution of the digital filter as well as to increase both the real time performance and the economical property. CONSTITUTION:In the digital filter, input signal Xi (the vector expressed by 8-bit parallel signal) is shifted via 1-bit shift circuit 1 and 2-bit shift circuit 2 each and then delivered. The signal delivered via FA22 (adder, full adder) becomes (1100), and the signal delivered via 2-bit shift circuits 23-25 become (0011)- (0001) respectively. As the signals to be opposed to (0000) are all zero, no input signal is necessary. And accordingly the 2-bit shift process and AF are not required. These signals are then supplied to matrix circuit 26 (comprising plural units of gate circuits and AF) which is state-set by tap coefficient Ci (i=0-m). |
