| 摘要 |
PURPOSE:To give a wide-synchronizing range and good jitter suppression characteristic in a digital phase synchronizing loop. CONSTITUTION:The phase difference between input and output clocks is detected by phase comparator 13. This phase difference is subjected to multilevel quantization in quantizing circuit 19 by fixed clocks from oscillator 16, and has the band limited by loop filter 14. The output of filter 14 is converted to a control signal, which has a phase control period corresponding to the phase difference above, in control period converter circuit 21. Stuffing or destuffing is performed in phase control circuit 15 for the fixed clock train from oscillator 16 by this control signal, and the fixed clock train is supplied to phase comparator 13 after frequency division in frequency divider 17. By this loop control, output clocks synchronizing with input clocks in phase can be obtained at terminal 18. |
