发明名称 SELECTIVE CONTROL SYSTEM FOR REGISTER
摘要 PURPOSE:To reduce the data length of an address register by using the head of a data part for its address when selecting several registers with shorter data length than that of an input data register. CONSTITUTION:To select several registers Ri0 to Ri2, and Rj0 to Rj2 with shorter data length than that of input data register 2, the head of data of the data register is used as part of an address and supplied to decoders 4 and 5, so that when those registers Ri0 to Ri2, and Rj0 to Rj2 are selected, the data length of the address register can be shortened. Those registers are grouped and the address register can select a specific register by selecting a corresponding group.
申请公布号 JPS5533246(A) 申请公布日期 1980.03.08
申请号 JP19780106075 申请日期 1978.08.30
申请人 FUJITSU LTD 发明人 SAGARA HISAJIROU
分类号 G06F7/00;G06F9/34;G06F12/00 主分类号 G06F7/00
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