| 摘要 |
PURPOSE:To reduce considerably the amount of hardware by using a memory as a variable delay circuit. CONSTITUTION:The write address and the read address are switched alternately by 2-1SEL (selector) 14 to write and read data alternately into and from random access memory RAM17 by four bits in parallel. The counted value of binary counter BCNT12 is increased or reduced by delay/advance instructions given from terminal 22, and multiplexer MUX20 is controlled by this counted value, thereby obtaining the delay quantity of a one-bit step. |
