Parallel digital data processing system with automatic fault recognition utilizing sequential comparators having a delay element therein

摘要

A digital data processing arrangement for railroad installations having two similarly designed sequential circuits employing microprocessors and operating in accordance with the 2v2-principle. A joint pulse current supply produces two control signal pairs which are displaced with respect to each other by at least one processing step, whereby the two sequential circuits which are processing the same information in relation to the respective processing phase exhibit a condition of inequality. Thereby, interferences simultaneously affecting the two sequential circuits in the same manner have a different readable effect. Specific comparators which take into consideration the condition of inequality are connected to similar inputs or outputs of the microprocessors. The comparison output of the comparators is interrogated by the pulse current supply after each processing step in a conjunctively linked manner. This leads to the release of an additional control signal pair required for the subsequent processing step. The pulse current supply is cut off when a faulty comparison is present.