发明名称 |
DYNAMIC RANDOM ACCESS MEMORY |
摘要 |
A memory in which each cell comprises an MOS transistor merged with a storage capacitor and in which the cells are arranged to permit adjacent pairs of transistors in a common column to share a common source and the transistors in a common row to share a common gate electrode conductor. The memory uses a first polycrystalline silicon layer which is patterned to provide interconnected storage electrodes and a second polycrystalline silicon layer which is patterned to provide a plurality of stripes to serve as the bit sense lines and a plurality of gate electrodes. |
申请公布号 |
GB2043999(A) |
申请公布日期 |
1980.10.08 |
申请号 |
GB19800015764 |
申请日期 |
1979.09.07 |
申请人 |
WE |
发明人 |
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分类号 |
G11C14/00;G11C11/40;H01L21/768;H01L21/82;H01L21/822;H01L21/8242;H01L23/535;H01L27/04;H01L27/06;H01L27/10;H01L27/108;(IPC1-7):01L21/82;11C11/40;01L27/10 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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