| 摘要 |
PURPOSE:To enhance the integration and to reduce the consuming electric power of the MIS transistors constituting the logic circuit by a method wherein a part of the semiconductor regions and the insulating layers of two MIS transistors are held in common. CONSTITUTION:A P-type region 33 and a P<+>-type region 34 are formed respectively in an N-type Si substrate 31 by diffusion, and an N<+>-type region 35 is provided in the region 33. Extending from the surface of a region 36 in the substrare 31 locating between the regions 33 and 34 to the surface of a region 37 in the neighboring region 33, these surfaces are covered with a united common insulating film 38, and a conductor layer 39 is formed on it. Constituting the circuit in this way, an N-channel type MIS transistor Q3 having the substrate 31 as the source, the region 35 as the drain, the region 37 as the channel, the layer 38 as the gate insulating layer and the layer 39 as the gate electrode layer, is constituted. A P-channel type MIS transistor Q4 having the region 33 as the source, the region 34 as the drain, the region 36 as the channel, the layer 38 as the insulating layer, the layer 39 as the gate electrode layer, is constituted and these transistors Q3 and Q4 are connected in the ordinary method. |
