发明名称 FORMING METHOD FOR RESISTANCE REGION
摘要 PURPOSE:To improve the accuracy of the value of resistance by a method wherein a resistance region is geometrically limited by V-grooves in which a heat resisting insulating material is filled when forming the resistance region of an integrated circuit device. CONSTITUTION:V-grooves 5 are made up on a semiconductor substrate 1 so as to limit an element region 2'. The difference of the speed of etching due to the difference of a surface direction of a substrate crystal is utilized for the formation of the V-grooves. A heat resisting insulating material 6, such as Si3N4, SiO2, Al2O3, etc. is filled in the V-grooves 5 by means of a CVD method. When forming resistance to the element region, ions are successively implanted to the element region, necessary impurities are introduced, and necessary resistance value is obtained. Thus, the element region is limited by the V-grooves, the element region do not vary in a process of heat treatment, and consequently resistance having high accuracy is acquired. Not only resistance but also other elements may similarly be made up in the element region. The V-grooves may be exchanged for U-grooves.
申请公布号 JPS5636149(A) 申请公布日期 1981.04.09
申请号 JP19790111155 申请日期 1979.08.31
申请人 FUJITSU LTD 发明人 SUDOU TAKEYUKI
分类号 H01L27/04;H01L21/822;H01L29/8605 主分类号 H01L27/04
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