| 摘要 |
PURPOSE:To realize a high speed and simplification for the process of multiplication for an operation controller that is formed into a chip with the high-integration semiconductor, by providing a means which delivers both the hihger and lower ranks of the result of operation in different timings at the inside multiplication function part. CONSTITUTION:In the initialization mode or the reading cycle mode, the gate circuit G1 opens by the control signal supplied from a 1-chip CPU101. Then the microinstruction read out of the external control memory part 102 is taken into the CPU101. In this case, the gate circuit G4 closes to isolate the common bus 103. Furthermore either one of the gate circuits G2 and G3 is opened selectively, and either one of the TEST0 and TEST1 external signal groups is taken into the CPU101 simultaneously with the microinstruction. The circuit G4 is opened in the modes other than the lead cycle mode, and the gate circuits G5-G7 are opened selectively to be connected selectively to the bus 103. Thus the data is transferred among the CPU101, address converting mechanism 105, main memory part and other input/output devices respectively. |
