发明名称 ADDRESS CONVERSION SYSTEM
摘要 PURPOSE:To make unnecessary address conversion by ROM, when the instruction group of other computer is emiluted, by mounting RAM to the lower rank address and ROM to the upper rank address, in a microprocessor. CONSTITUTION:CPU1 is set to initial state with clear signal CLR, the output signal Q of FF2 is at L(low) level, and the output signal lines A14', A15' of the NOR gates 31, 32 are at H(high) level. When CPU1 outputs the memory address 0000H to the address buses A08-A15 and AD00-AD07 to read out program from ROM, the output address of 8 upper rank address buses are 0000H of the lines A15', A14', A13-A08, and CPU1 executes program from this address. When FF2 is set with the write instruction WR, the output Q is at H level, since the buses A14, A15 are at L level, the output of the gates 31, 32 is changed to L level via the inverters 34, 35 and the address of CPU designates the RAM address of lower rank address.
申请公布号 JPS56137458(A) 申请公布日期 1981.10.27
申请号 JP19800040219 申请日期 1980.03.31
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 NAKAMURA TOKUMITSU
分类号 G06F12/06;G06F9/06;G06F9/445;G06F12/02 主分类号 G06F12/06
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