| 摘要 |
PURPOSE:To cope with various different speeds of transmission in an octet time- division multiplex system, by adding a timing control circuit and a bit control circuit. CONSTITUTION:A circuit that inhibits an FRM is provided by adding a circuit which inhibits the 17FRM by means of an n-bit shift register NBITSR and a decoder DECODE. Then the data is stored in the BUFF as if the data were given to a data buffer even during the 17FRM, and thus an amount equivalent to the 17FRM can be supplemented. In such a way, the data is received from a data highway with an even interval. |
