| 摘要 |
PURPOSE:To make phase of two signals match, by inputting a correcting signal into differential pulse width of one signal, and mixing this correcting signal with said signal. CONSTITUTION:The first signal (a) is inputted from a terminal 1. The second signal (c) is obtained by dividing a pulse of an oscillator 21 by frequency dividers 22, 23. A correction logical circuit 3 is operated in order to make phase of the second signal (c) match that of the first signal (a), forms a correcting signal (h) from a differential pulse (d) which is obtained by a differentiating circuit 31, mixes the correcting signal (h) with an output (i) of the frequency divider 22, and applies it to the frequency divider 23. In case when the second signal (c) leads the first signal (a) in phase, an AND signal (e) of a differential signal (d), and a reverse signal (b) of the first signal (a) becomes a correcting signal through an OR gate 35, and phase of the second signal (c) lags. In case when the second signal (c) lags in phase, an output (f) of the oscillator 21 is inserted into the differential pulse width, becomes a correcting signal, and makes its phase proceed. |
